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| FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator August 2009 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Features Single-Supply Operation with 4A Output Current Wide Input Range with Dual Supply: 3.0V to 24V Wide Output Voltage Range: 0.8V to 80% VIN Over 94% Peak Efficiency 1% Reference Accuracy Over Temperature Fully Synchronous Operation with Integrated Schottky Diode on Low-Side MOSFET Boosts Efficiency Single Supply Device for VIN > 6.5V - 24V Programmable Frequency Operation (200600KHz) Synchronizable to External Clock with Master/Slave Provisions Power-Good Signal Accepts Ceramic Capacitors on Output External Compensation for Flexible Design Starts on Pre-Bias Outputs Integrated Bootstrap Diode Programmable Over-Current Protection Under-Voltage, Over-Voltage, and ThermalShutdown Protections 5x6mm, 25-Pin, 3-Pad MLP Package Description The FAN21SV04 TinyBuckTM is a highly efficient, small-footprint, programmable-frequency, 4A, integrated synchronous buck regulator. FAN21SV04 contains both synchronous MOSFETs and a controller/driver with optimized interconnects in one package, which enables designers to solve highcurrent requirements in a small area with minimal external components, thereby reducing cost. Onboard internal 5V regulator enables single-supply operation for input voltages >6.5V. The FAN21SV04 can be configured to drive multiple slave devices OR synchronize to an external system clock. In slave mode, FAN21SV04 may be set up to be free-running in the absence of a master clock signal. External compensation, programmable switching frequency, and current-limit features allow for design optimization and flexibility. High-frequency operation allows for all-ceramic solutions. Fairchild's advanced BiCMOS power process, combined with low-RDS(ON) internal MOSFETs and a thermally efficient MLP package, provide the ability to dissipate high power in a small package. Integration helps minimize critical inductances, making layout simpler and more efficient compared to discrete solutions. Output over-voltage, under-voltage, over-current, and thermal-shutdown protections help protect the device from damage during fault conditions. FAN21SV04 prevents pre-biased output discharge during startup in point-of-load applications. Applications Servers & Telecom Graphics Cards & Displays Computing Systems Set-Top Boxes & Game Consoles Point-of-Load Regulation Related Application Notes AN-8022 -- TinyCalcTM Calculator Ordering Information Part Number FAN21SV04MPX FAN21SV04EMPX Operating Eco Temperature Range Status -10C to 85C -40C to 85C Green Green Package Packing Method Molded Leadless Package (MLP) 5x6mm Tape and Reel Molded Leadless Package (MLP) 5x6mm Tape and Reel For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Typical Application Diagram Figure 1. Typical Application as Master at VIN=6.5V to 24V Block Diagram Figure 2. Block Diagram (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 Reg www.fairchildsemi.com 2 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Pin Configuration Figure 3. MLP 5x6mm Pin Configuration (Bottom View) Pad / Pin Definitions Pad / Pin P1, 6-12 P2, 3-5 P3, 21-23 1 Name SW VIN PGND BOOT Description Switching Node. Junction of high-side and low-side MOSFETs. Power Conversion Input Voltage. Connect to the main input power source. Power Ground. Power return and Q2 source. High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC has an internal synchronous bootstrap diode to recharge the capacitor on this pin to 5V_Reg when SW is LOW. Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage >6.5V with 10 resistor and a 1F bypass capacitor at the pin (see Figure 10). Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is outside the specified limits. PGOOD does not assert HIGH until the fault latch is enabled (see Figure 31). ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the regulator after a latched-fault condition. This input has an internal pull-up. When a latched fault occurs, EN is discharged by a current sink. 5V Regulator Output. Internal regulator output that provides power for the IC's logic and analog circuitry. This pin should be connected to AGND through a >2.2f X5R/X7R capacitor. Analog Ground. The signal ground for the IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection. Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the internal default setting. Switching Frequency and Master/Slave Set. Connecting a resistor (RT) to AGND sets the switching frequency and configures the CLK pin as an output (master). Tying this pin to 5V_Reg through a resistor configures the CLK signal as an input (slave) and establishes the free-running switching frequency. Output Voltage Feedback. Connect through a resistor divider to the output voltage. Compensation. Error amplifier output. Connect the external compensation network between this pin and FB. Clock. Bi-directional signal pin, depending on master/slave configuration. When configured as a master, this pin represents the clock output that connects directly to the slave(s) for synchronizing with 180 phase shift. Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the internal ramp amplitude and also provides voltage feedforward functionality. 2 VIN_Reg 13 PGOOD 14 EN 15 16 17 5V_Reg AGND ILIM 18 19 20 24 25 RT FB COMP CLK RAMP (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 3 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VIN, VIN_Reg to AGND AGND=PGND 5V_Reg to AGND BOOT to PGND BOOT to SW SW to PGND All other pins ESD Electrostatic Discharge Protection Level Continuous AGND=PGND Conditions Min. Max. 28 6 35 Units V V V V V V kV -0.5 -0.5 -5 -0.3 Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 1.5 2.5 Transient (t < 20ns, f < 600KHz) 6.0 24.0 30 6.0 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol fSW VIN, VIN_Reg TA TJ Parameter Switching Frequency Supply Voltage for Power and Bias Ambient Temperature Junction Temperature Conditions VIN to PGND VIN_Reg to AGND FAN21SV04MPX FAN21SV04EMPX Min. 200 3.0 6.5 -10 -40 Typ. 500 Max 600 24.0 24.0 +85 +85 +125 Units KHz V C C Thermal Information Symbol TSTG TL JC J-PCB PD Storage Temperature Lead Soldering Temperature, 30 Seconds P1 (Q2) Thermal Resistance: Junction-to-Case P2 (Q1) P3 Thermal Resistance: Junction-to-Mounting Surface Total Power Dissipation in the package, TA=25C (1) (1) Parameter Min. -65 Typ. Max. +150 +300 Units C C C/W C/W 4 7 4 35 2.8 W Note: 1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 38. Actual results are dependent upon mounting method and surface related to the design. (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 4 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Electrical Characteristics Recommended operating conditions and using the circuit shown in Figure 1, with VIN, VIN_Reg=12V, unless otherwise noted. Parameter Power Supplies Operating Current (VIN+VIN_Reg) VIN_Reg Operating Current VIN_Reg Quiescent Current VIN_Reg Standby Current 5V_Reg Output Voltage 5V_Reg Max. Current Load VIN_Reg UVLO Threshold Reference Reference Voltage measured at FB (See Figure 4 for Temperature Coefficient) Oscillator Frequency Frequency in Slave Mode Compared to Master Mode Minimum On Time Duty Cycle Ramp Amplitude, (2) Peak-to-Peak (2) Minimum Off Time Synchronization CLK Output Pulse Width CLK Output Sink Current CLK Output Source Current CLK Input Pulse Width CLK Input Source Current CLK Input Threshold, Rising Soft-Start VOUT to Regulation (T0.8) Fault Enable/SSOK (T1.0) Error Amplifier (2) DC Gain (2) Gain Bandwidth Product Output Voltage Swing (VCOMP) Output Current, Sourcing Output Current, Sinking FB Bias Current (2) Conditions VIN=12V, 5V_Reg Open, CLK Open, fSW =500KHz, No Load EN=High, 5V_Reg Open, CLK Open, fSW =500KHz EN=High, FB=0.9V EN=0, VIN=12V Internal VCC Regulator, No Load, 6.5V Min. Typ. 22 11 4 Max. 30 Units mA mA 5 1 5.3 5 6.3 5 806 805 mA mA V mA V V 4.7 5.0 5.6 794 795 800 800 mV RT=50k to GND (Master Mode) RT=24k to GND (Master Mode) RT=24 k to 50k to 5V_Reg (Slave Mode) VIN=6.5V, fSW =600KHz VIN=16V, 1.8VOUT, RT=30k, RRAMP=200k 255 540 -15 300 600 345 660 +15 KHz % ns % V 40 80 0.5 100 65 85 150 100 0.35 -2.0 -170 1.93 ns ns mA mA ns A V ms ms dB MHz V mA mA nA Master (RT to GND) Master, VCLK=0.4V Master, VCLK=2V Slave: VCLK > 2V Slave: VCLK=1V Slave 70 0.25 -2.5 50 -230 1.73 85 -200 1.83 2.5 3.1 Frequency=500KHz VIN_Reg > 6.5V 5V_Reg=5V, VCOMP=2.2V 5V_Reg=5V, VCOMP=1.2V VFB=0.8V, TA=25C 80 12 0.4 1.5 0.8 -850 85 15 2.2 1.2 -650 4.0 2.5 1.5 -450 Note: 2. Specifications guaranteed by design and characterization; not production tested. (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 5 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Electrical Characteristics (Continued) Recommended operating conditions and using the circuit shown in Figure 1 with VIN, VIN_Reg=12V, unless otherwise noted. Parameter Control Functions EN Threshold, Rising EN Hysteresis EN Pull-Up Resistance EN Discharge Current FB OK Drive Resistance PGOOD Low Threshold PGOOD Low Voltage PGOOD Leakage Current Protection and Shutdown Current Limit Conditions Min. Typ. 1.35 250 800 1 800 -11.0 +10.0 0.2 Max. 2.00 Units V mV K A VIN_Reg >6.5V Auto-Restart Mode, VIN_Reg>6.5V FB < VREF, 2 Consecutive Clock Cycles (3) FB > VREF, 2 Consecutive Clock Cycles IOUT < 2mA VPGOOD=5V RILIM open, fSW =500KHz, VOUT=1.8V, RRAMP=200k, 16 Consecutive Clock (3) Cycles VIN_Reg > 6.5V, TA=25C (3) -14.0 +7.0 1000 -8.0 +13.5 0.4 1.0 K %VREF V A 5.5 -11 6.5 -10 +155 +30 115 73 250 250 7.5 -9 A A C C %VOUT %VOUT mV mV ILIM Current Over-Temperature Shutdown Internal Temperature Over-Temperature Hysteresis (3) Over-Voltage Threshold 2 Consecutive Clock Cycles (3) Under-Voltage Shutdown 16 Consecutive Clock Cycles Fault-Discharge Threshold Measured at FB pin Fault-Discharge Hysteresis Measured at FB pin (VFB ~500mV) 110 68 120 78 Note: 3. Delay times are not tested in production. Guaranteed by design. (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 6 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Typical Characteristics VIN=12V, VCC=5V, TA=25C, unless otherwise specified. 1.010 1.005 V FB 1.000 0.995 0.990 -50 0 50 Temperature (oC) 100 150 1.20 1.10 I FB 1.00 0.90 0.80 -50 0 50 Temperature (oC) 100 150 Figure 4. Reference Voltage (VFB) vs. Temperature, Figure 5. Reference Bias Current (IFB) vs. Temperature, Normalized Normalized 1500 1200 900 600 300 0 0 20 40 60 80 100 120 140 RT (K) 1.02 Frequency (KHz) 1.01 Frequency 600KHz 1.00 300KHz 0.99 0.98 -50 0 50 Temperature ( C) o 100 150 Figure 6. Frequency vs. RT (Master) Figure 7. Frequency vs. Temperature, Normalized 1.60 1.40 I ILIM 1.04 1.02 1.00 0.98 0.96 RDS 1.20 1.00 Q1 ~0.32 %/ C 0.80 0.60 -50 0 50 Temperature ( C) o o Q2 ~0.35 %/ C 100 150 -50 0 50 Temperature ( C) o o 100 150 Figure 8. RDS vs. Temperature, Normalized (5V_Reg=VGS=5V) Figure 9. ILIM Current (IILIM) vs. Temperature, Normalized (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 7 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Application Circuit FAN21SV04 Figure 10. Single-Supply Application Circuit: 1.8VOUT, 500KHz, Master, 8V - 20V Input FAN21SV04 Figure 11. Single -Supply Application Circuit: 1.2 VOUT, 500KHz, Master 8V - 20V Input (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 8 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Typical Performance Characteristics Typical operating characteristics using the Figure 10 circuit; VIN=12V, VCC=5V, TA=25C, unless otherwise specified. 95 1.8V_Eff 8-20V_500kHz 90 95 3.3V Eff 8-20V 500kHz 90 Efficiency(%) 85 Efficiency(%) 85 8Vin 12Vin 80 8V 12V 75 16V 20V 70 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 80 16Vin 75 20Vin 70 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 Figure 12. 95 1.8 VOUT Efficiency Over VIN vs. Load Figure 13. 3.3 VOUT Efficiency, 500KHz (4) 1.8V_Eff 8-20V_300kHz 90 95 3.3V_Eff 8-20V_300kHz 90 Efficiency(%) 85 Efficiency(%) 85 80 8V 12V 16V 8V 80 12V 75 16V 20V 70 75 20V 70 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 Figure 14. 1.8 VOUT Efficiency, 300KHz 95 (4) Figure 15. 3.3 VOUT Efficiency, 300KHz (4) 1.2V_Eff 8-20V_500kHz 95 90 90 Efficiency (%) 85 Efficiency(%) 85 5V_Eff 8-20V_300kHz 80 8Vin 80 12Vin 16Vin 75 20Vin 8V 75 12V 16V 20V 70 0 0.5 1 1.5 2 Load (A) 2.5 3 3.5 4 70 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 Figure 16. 1.2 VOUT Efficiency, 500KHz (Figure 11) Note: 4. Circuit values for this configuration change in Figure 10. Figure 17. 5 VOUT Efficiency, 300KHz (4) (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 9 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Typical Performance Characteristics (Continued) Typical operating characteristics using the Figure 10 circuit; VIN=12V, VCC=5V, TA=25C, unless otherwise specified. 0.10 Line Regulation 0.08 No load 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0 5 10 15 Input Voltage (V) 20 25 0.5A Load 0.15 Load Regulation % Change in output voltage as compared at 0 Amps 0.1 12V 0.05 16V % Change in output voltage as compared to set value at 6.5V 0 -0.05 -0.1 -0.15 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 Figure 18. 70 1.8 VOUT Line Regulation 70 Figure 19. 1.8 VOUT Load Regulation 60 Peak Case Tempr over Mosfet Location @Room Tempr - 3.3V Output, 500kHz 60 Temperature (Deg C) 40 Temperature (Deg C) 50 50 Peak Case Tempr over Mosfet Location @Room Tempr - 5V Output, 300kHz 40 30 12V_HS 12V_LS 24V_HS 30 20 20 12V_HS 10 24V_LS 10 12V_LS 0 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 0 0 0.5 1 1.5 2 Load(A) 2.5 3 3.5 4 Figure 20. Peak MOSFET Temperatures (5) 3.3V Output, 12V and 24V Input (500KHz) 95 Figure 21. Peak Case Temperature Over MOSFET Locations 5V Output (300KHz) Recommended FAN21SV04 Safe Operating Area curves for 70 Deg Temperature rise VIN = 20V, Natural Convection. 1.8 V_ Eff 1 2V Input 90 6 5 85 Efficiency(%) 300kHz 400kHz 80 500kHz 600kHz 75 Load Current (Amps) 4 3 2 300KHz 1 0 500KHz 600Khz 70 0 0.5 1 1.5 2 Lo ad(A) 2.5 3 3.5 4 0 2 4 6 8 10 12 14 Output Voltage (Volts) Figure 22. 1.8 VOUT Efficiency Over fSW Figure 23. Typical Output Operating Area Based on Thermal Limitations Note: 5. Circuit values for this configuration change in Figure 10. (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 10 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Typical Performance Characteristics (Continued) Typical operating characteristics using the Figure 10 circuit. VIN=12V unless otherwise specified. VOUT, 1V/div EN, 1V/div CLK, 5V/div VOUT, 100mv/div IOUT, 2A/div PGOOD, 5V/div Figure 24. CLK and VOUT at Startup Figure 25. Transient Response, 2-4A Load VOUT, 1V/div EN, 2V/div SW, 10V/div SW, 10V/div Figure 26. Startup on Pre-Bias Figure 27. Restart on Fault CLK, 5V/div VOUT, 1V/div CLK, 5V/div EN, 5V/div SW, 5V/div PGOOD, 5V/div Figure 28. Shutdown, 1A Load Figure 29. Slave (500KHz Free-Run to 600KHz Synchronization) (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 11 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Circuit Operation PWM Generation Refer to Figure 2 for the PWM control mechanism. FAN21SV04 uses the summing-mode method of control to generate the PWM pulses. An amplified currentsense signal is summed with an internally generated ramp and the combined signal is compared with the output of the error amplifier to generate the pulse width to drive the high-side MOSFET. Sensed current from the previous cycle is used to modulate the output of the summing block. The output of the summing block is also compared against a voltage threshold set by the RLIM resistor to limit the inductor current on a cycle-bycycle basis. RRAMP resistor helps set the charging current for the internal ramp and provides input voltage feed-forward function. The controller facilitates external compensation for enhanced flexibility. Internal Regulator FAN21SV04 facilitates single-supply operation for input voltages >6.5V. At startup, the output of the internal regulator tracks the input voltage and comes into regulation (5V) when VIN_Reg exceeds the UVLO threshold. The EN pin is released at the same time. The output voltage of the internal regulator (5V_Reg) is set to 5V. The internal regulator supplies power to all the control circuits including the drivers. For applications with VIN<6.5V, FAN21SV04 can be used if VIN_Reg is provided with a separate low-power source >6.5V. VIN_Reg supply should come up after VIN during dual-supply operation. The VIN_Reg pin should always be decoupled with at least a 10 resistor and a 1F ceramic capacitor (see Figure 10, Figure 11). Since 5V_Reg is used to drive the internal MOSFET gates, high peak currents are present on the 5V_Reg pin. Connect a >2.2f X5R or X7R decoupling capacitor between the 5V_Reg pin and AGND. For VIN>20V operation, use a 3.3 resistor in series with the boot capacitor to reduce noise into the regulator. In addition to supplying power for the control circuits internally, 5V_Reg output can be used as a reference voltage for other applications requiring low noise reference voltage. 5V_Reg is capable of sourcing up to 5mA of output current. When EN is pulled LOW externally, 5V_Reg output is still present, but the IC is in standby mode with no switching. Initialization Once VIN_Reg voltage exceeds the UVLO threshold and EN is HIGH, the IC checks for a shorted FB pin before releasing the internal soft-start ramp (SS). If the parallel combination of R1 and RBIAS is 1k, the internal SS ramp is not released and the regulator does not start. Enable FAN21SV04 has an internal pull-up to the enable (EN) pin so that the IC is enabled once VIN_Reg exceeds the UVLO threshold. Connecting a small capacitor across EN and AGND delays the rate of voltage rise on the EN pin. The EN pin also serves for the restart whenever a fault occurs (refer to the Auto-Restart section). If the regulator is enabled externally, the external EN signal should go HIGH only after 5V_Reg is established. For applications where such sequencing is required, FAN21SV04 can be enabled (after the VCC comes up) with external control, as shown in Figure 30. If auto-restart is not desired, tie the EN pin HIGH with a logic gate to keep the 1A current sink from discharging EN to 1.1V. Figure 32 shows one method to pull up EN to VCC for a latch configuration. Soft-Start FAN21SV04 uses an internal digital soft-start circuit to slowly ramp up the output voltage and limit inrush current during startup. When 5V_Reg is in regulation and EN is HIGH, the circuit releases SS and enables the PWM regulator. Soft-start time is a function of the switching frequency (number of clock cycles). Once internal SS ramp has charged to 0.8V (T0.8), the output voltage is in regulation. Until SS ramp reaches 1.0V (T1.0), only the over-current-protection circuit is active during soft-start and all other output protections are inhibited. In dual-supply operation mode, it is necessary to apply VIN before VIN_Reg reaches its UVLO threshold to avoid skipping the soft-start cycle. VIN_Reg UVLO or toggling the EN pin discharges the SS and resets the IC. Figure 30. Enabling with External Control (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 12 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Over-Temperature Protection The chip incorporates an over-temperature protection circuit that sets the fault latch when a die temperature of about 155C is reached. The IC is allowed to restart when the die temperature falls below 125C. Auto-Restart After a fault, the EN pin is discharged with 1A current pull-down to a 1.1V threshold before the internal 800k pull-up is restored. A new soft-start cycle begins when EN charges above 1.35V. Depending on the external circuit, the FAN21SV04 can be configured to remain latched off or automatically restart after a fault, as listed in Table 1. Table 1. EN Pin Fault / Restart Configurations Controller / Restart State OFF (Disabled) No Restart - Latched OFF Immediate Restart After Fault New Soft-Start Cycle After EN is HIGH (Auto Restart Mode) Pull to GND Connected to 5V_Reg with 100K Open Cap to GND Figure 31. Typical Soft-Start Timing Diagram With EN left open, restart is immediate. If auto-restart is not desired, tie the EN pin HIGH with a logic gate to keep the 1A current sink from discharging EN to 1.1V. Figure 32 shows one method to pull up EN to VCC for a latch configuration. Startup on Pre-Bias The regulator does not allow the low-side MOSFET to operate in full synchronous mode until SS reaches 95% of VREF (~0.76V). This enables the regulator to startup on a pre-biased output and ensures that output is not discharged during the soft-start cycle. Protections The converter output is monitored and protected against extreme overload, short-circuit, over-voltage, and under-voltage conditions. Under-Voltage Protection If FB remains below the under-voltage threshold for 16 consecutive clock cycles, the fault latch is set and the converter shuts down. This protection is not active until the internal SS ramp reaches 1.0V during soft-start. Over-Voltage Protection If FB exceeds 115% * VREF for two consecutive clock cycles, the fault latch is set and shutdown occurs. A shorted high-side MOSFET condition is detected when SW voltage exceeds ~0.7V while the low-side MOSFET is fully enhanced. The fault latch is set immediately upon detection. The OV/UV fault conditions are not allowed to set the fault latch during soft-start. They are active only after T1.0 (see Figure 31). Figure 32. Enable Control with Latch Option Power Good (PGOOD) Signal PGOOD is an open-drain output that asserts LOW when VOUT is out of regulation, as measured at the FB pin. The thresholds are specified in the Electrical Specifications section. PGOOD does not assert HIGH until soft start is complete (T1.0) (see Figure 31). (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 13 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Application Information 5V_Reg Output The 5V_Reg pin is the output of the internal regulator that supplies all power to the control circuit. It is important to keep this pin decoupled to AGND with a >2.2f X5R or X7R decoupling capacitor. In addition, for operation with VIN>20V, add a 3.3 resistor in series with the boot capacitor to reduce the switching noise into the regulator. transient response use a higher ripple-current setting while regulator designs that require higher efficiency keep ripple current on the low side and operate at a lower switching frequency. The inductor value is calculated by the following formula: VOUT * (1 L= VOUT ) VIN IL * f (3) Setting the Output Voltage The output voltage of the regulator can be set from 0.8V to ~80% of VIN by an external resistor divider (R1 and RBIAS in Figure 1). For output voltages >3.3V, output current rating may need to be de-rated depending on the ambient temperature, power dissipated in the package, and the PCB layout (refer to Thermal Information table on page 4, Figure 20, Figure 21, and Figure 23). The internal reference is set to 0.8V with 650nA sourced from the FB pin to ensure that the regulator does not start if the pin is left open. The external resistor divider is calculated using: V - 0 .8 V 0 .8 V = OUT + 650nA R BIAS R1 where f is the switching frequency. Setting the Ramp Resistor Value RRAMP resistor plays a critical role by providing charging current to the internal ramp capacitor and also serving as a means to provide input voltage feedforward. RRAMP is calculated by the following formula: R RAMP (K ) = (30 .5 - 4.5 * IOUT ) * VIN * f * 10 - 6 ( VIN - 1.8 ) * VOUT -2 (4) where frequency (f) is expressed in KHz. For wide input operation, first calculate RRAMP for the minimum and maximum input voltage conditions and use larger of the two values calculated. (1) Connect RBIAS between FB and AGND. If R1 is open (see Figure 1), the output voltage is not regulated and a latched fault occurs after the SS is complete (T1.0). If the parallel combination of R1 and RBIAS is 1K, the internal SS ramp is not released and the regulator does not start. In all applications, current through the RRAMP pin must be greater than 10A from the equation below for proper operation: VIN - 1.8 10 A RRAMP + 2 (5) Setting the Switching Frequency Switching frequency is determined by a resistor, RT, connected between the RT pin and AGND (Master Mode) or 5V_Reg (Slave Mode): where RT is expressed in k: RT ( K ) = (106 / f ) - 135 65 If the calculated RRAMP values in Equation (4) result in a current less than 10A, use the RRAMP value that satisfies Equation (5). In applications with large Input ripple voltage, the RRAMP resistor should be adequately decoupled from the input voltage to minimize ripple on the ramp pin. Setting the Current Limit There are two levels of current-limit thresholds in FAN21SV04. The first level of protection is through an internal default limit set at the factory to provide cycleby-cycle current limit and prevent output current beyond normal levels. The second level of protection is set at the ILIM pin by connecting a resistor (RILIM) between ILIM and AGND. Current-limit protection is enabled whenever the lower of the two thresholds is reached (see Figure 33). The FAN21SV04 uses its internal low-side MOSFET as the current-sensing element. The current-limit threshold voltage (VILIM) is compared to the voltage drop across the low-side MOSFET sampled at the end of each PWM off-time cycle. The internal default threshold (ILIM open) is temperature compensated. (2) where frequency (f) is expressed in KHz. In Slave Mode, the switching frequency is about 10% slower for the same RT. The regulator does not start if RT is open in Master Mode. Calculating the Inductor Value Typically the inductor value is chosen based on ripple current (IL), which is chosen between 10 to 35% of the maximum DC load. Regulator designs that require fast (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 14 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Since the FAN21SV04 employs summing current-mode architecture, Type-2 compensation can be used for many applications. For applications that require wide loop bandwidth and/or use very low-ESR output capacitors, Type-3 compensation may be required. RRAMP provides feedforward compensation for changes in VIN. With a fixed RRAMP value, the modulator gain increases as VIN is reduced, which can make it difficult to compensate the loop. For low-input-voltage-range designs (3V to 8V), RRAMP and the compensation component values are different as compared to designs with VIN between 8V and 24V. Figure 33. ILIM Network Master / Slave Configuration When first enabled, the IC determines if it is configured as a master or slave for synchronization, depending on how RT is connected. The ILIM pin can source a 10A current that can be used to establish a lower, temperature-dependent, current-limit threshold by connecting an external resistor (RILIM) to AGND. RILIM can be approximated with the equation: (V - 1.8) * VOUT * 3.33 * 106 RILIM(K) = 95 + 15.1* IOUT + IN (RRAMP + 2) * VIN * f Table 2. RT to: Master / Slave Configuration Master / Slave CLK Pin (6) where: IOUT = VOUT = VIN = RRAMP = f = GND Full load current in Amps; Set output voltage; Input voltage; Ramp resistor used in K; and Selected switching frequency in KHz. 5V_Reg Master Slave, free-running Output Input After 16 consecutive pulse-by-pulse current-limit cycles, the fault latch is set and the regulator shuts down. Cycling VIN_Reg or EN restores operation after a normal softstart cycle (refer to the Auto-Restart section). The over-current protection fault latch is active during the soft-start cycle. Use a 1% resistor for RILIM. For a given RRAMP and RILIM setting, the current-limit point varies slightly in an inverse relationship to VIN. If RILIM is not connected, the IC uses the internal default currentlimit threshold. Slaves free-run in the absence of an external clock signal input when RT is connected to 5V_Reg, allowing regulation to be maintained. It is not recommended to leave RT open when running in Slave Mode to avoid noise pick up on the clock pin. Slave free-running frequency should be set at least 25% lower than the incoming synchronizing pulse frequency. Maximum synchronizing clock frequency is recommended to be below 600KHz. Synchronization The synchronization method employed by the FAN21SV04 also provides the following features for maximum flexibility. Synchronization to an external system clock Multiple FAN21SV04s can be synchronized to a single master or system clock Independently programmable phase adjustment for one or multiple slaves Free-running capability in the absence of system clock or, if the master is disabled/faulted, the slaves can continue to regulate at a lower frequency The FAN21SV04 master outputs an 85ns-wide clock o (CLK) signal, delayed 180 from its leading PWM edge. This feature allows out-of-phase operation for the slaves, thereby reducing the input capacitance requirements when more than one converter is operating on the same input supply. The leading SW-node edge is delayed ~40ns from the rising PWM signal. On a slave, synchronization is rising-edge triggered. The CLK input pin has a 1.8V threshold and a 200A current source pull-up. Loop Compensation The control loop is compensated using a feedback network around the error amplifier. Figure 34 shows a complete Type-3 compensation network. Type-2 compensation eliminates R3 and C3. COMP C2 C1 R2 R1 VREF FB R3 C3 R3 RBIAS VOUT Figure 34. Compensation Network (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 15 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator In Master Mode, the clock signals go out after powergood signal asserts HIGH. Likewise, in Slave Mode, synchronization to an external clock signal occurs after the power-good signal goes HIGH. Until then, the converter operates in free-run mode. PCB Layout Good PCB layout and careful attention to temperature rise is essential for reliable operation of the regulator. Four-layer PCB with two-ounce copper on the top and bottom side and thermal vias connecting the layers is recommended. Keep power traces wide and short to minimize losses and ringing. Do not connect AGND to PGND below the IC. Connect AGND pin to PGND at the output OR to the PGND plane. Figure 35. Synchronization Timing Diagram VIN SW PGND PGND VOUT Figure 36. Slave-CLK-Input Block Diagram Figure 38. Recommended PCB Layout One or more slaves can be connected directly to a o master or system clock to achieve a 180 phase shift. Figure 37. Slaves with 180 Phase Shift o Since the synchronizing circuit utilizes a narrow reset o pulse, the actual phase delay is slightly more than 180 . The FAN21SV04 is not intended for use in singleoutput, multi-phase regulator applications. (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 16 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator Physical Dimensions 2X TOP VIEW 2X RECOMMENDED LAND PATTERN ALL VALUES TYPICAL EXCEPT WHERE NOTED SIDE VIEW SEATING PLANE OPTIONAL LEAD DESIGN (LEADS# 1, 24 & 25 ONLY) SCALE: 1.5X BOTTOM VIEW A) DIMENSIONS ARE IN MILLIMETERS. B) DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) DESIGN BASED ON JEDEC MO-220 VARIATION WJHC E) TERMINALS ARE SYMMETRICAL AROUND THE X & Y AXIS EXCEPT WHERE DEPOPULATED. F) DRAWING FILENAME: MKT-MLP25AREV3 Figure 39. 5x6mm Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 17 FAN21SV04 -- TinyBuckTM 4A, 24V Single-Input Integrated Synchronous Buck Regulator (c) 2009 Fairchild Semiconductor Corporation FAN21SV04 * Rev. 1.0.1 www.fairchildsemi.com 18 |
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